As is known in the art, a cascode amplifier may be fanned with either Field Effect Transistors (FETs) or Bipolar Junction Transistors (BJTs). In the case of a FET a gate is used as a control electrode for controlling a flow of carriers between a source electrode and a drain electrode and in the case of a BJT a base electrode is used as a control electrode to control a flow of carriers between a collector electrode and a drain electrode. Thus, it should be noted that while a FET cascode amplifier is described, the material can be equivalently applied to a BJT. Thus, the gate electrode of a FET is equivalent to a base electrode of a BJT; either being referred to herein as a control electrode for the transistor. In like manner the terms drain and source may be interchanged for a FET as well as the terms emitter and collector for a BJT.
Thus, considering a Field Effect Transistor (FET) cascode amplifier, such FET cascode amplifier includes a common source (CS) connected FET serially connected to a common gate (CG) connected FET with the drain of the CS FET being coupled to the source of the CG FET; the drain of the common gate (CG) FET being coupled to a Vdd voltage supply. In a typical cascode arrangement, the sizes of the CS and CG FETs are equal (i.e. the total gate widths for the two transistors are the same Wg_cs=Wg_cg).
In general, DC biasing circuit or regulators, in order to operate effectively, must provide DC bias regulation (i.e. produce gate DC bias voltages for the CS and CG FETS or base DC bias voltages for BJTs) in such a way that the cascode amplifier performance (measured by DC drain/collector current, RF gain, noise figure, output power, linearity) is insensitive to variation in manufacturing process, temperature and external DC bias voltage. The first two variations typically manifest themselves as variations in transistor pinch off, Vp, or threshold voltage.
An additional requirement, specific to a cascode amplifier, is a controlled division of Vdd (or Vcc for a bipolar cascode amplifier) between the drain to source voltage (Vds) of the common gate FET (Vds_cg) drain-source junction and the drain to source voltage of the common source FET (Vds_cs) drain-source junction in order to ensure that both FETs are always in the saturation regime (Vds>VKnee), (where Vknee is the voltage at the knee of the saturation curve) so that the drain to source current (Ids) is nearly independent of Vds for both transistors in the cascode). For example, if Vdd=2V and VKnee=0.5V, one would like to avoid situations when Vds_cg=0.4V and Vds_cs=1.6V or Vds_cg=1.6V and Vds_cs=0.4V. Also, as is known in the art, the equal division results in the maximum output power and linearity of a cascode amplifier. Thus, a DC bias regulator for a cascode amplifier should be capable of enforcing a condition wherein the drain-source voltages for the common -source and common-gate (common-emitter and common-base) transistors are equal by design and remain equal in presence of variation in manufacturing process, temperature and external DC bias voltage.
One DC bias regulator for a cascode transistor amplifier is described in U.S. Pat. No. 5,032,799 inventor Milberger, et al., entitled “Multistage cascode radio frequency amplifier” issued Jul. 16, 1991. However, such DC bias regulator is a passive DC bias regulator circuit and therefore does not provide compensation for variations in manufacturing process, temperature and external DC bias voltage. Two active DC bias regulators are described in U.S. Pat. No. 5,506,544, inventor Staudinger et al., entitled “Bias Circuit for Depletion Mode Field Effect Transistors”, issued Apr. 9, 1996 and in U.S. Pat. No. 7,961,049, Busking et al., entitled “Amplifier with compensated gate bias”, issued Jun. 14, 2011; while these two DC bias regulators do compensate for process condition variations, they are specific for a common source FET and are used to maintain constant drain current through that single FET and not applicable for a cascode amplifier having a pair of FETs.
As is also known in the art, it is sometimes required that resistors used in an integrated circuit have a precise predetermined relationship in the value of their resistances for the circuit to operate properly. It is also known in the art that it is easier to fabricate resistor of equal resistance as compared fabricating resistors requiring a predetermined difference in resistance for proper operation of a circuit.
As is also known in the art, one circuit shown in FIG. 1, used to combine a pair of input voltages in a so-called Millman “Passive Averager”, is described in an article entitled “A Useful Network Theorem” by Jacob Millman, published in the Proceedings of the IRE, September 1940, pages 413-471. As described therein, in a specific case an output voltage Vout is produced from a pair of input voltages Vx and Vy:
      V    out    =                                          V            x                                R            x                          +                              V            y                                R            y                                                1                      R            x                          +                  1                      R            y                                =                                        V            x                    ⁢                      R            y                          +                              V            y                    ⁢                      R            x                                                R          x                +                  R          y                    
and in the specific case where Rx=Ry;
      V    out    =                    V        x            +              V        y              2  
As is also known in the art, multi-stage amplifier may include a cascode amplifier as one of the stage therein. Thus, proper isolation between stages is required as well as proper DC biasing of the cascode stage. Thus, here again, a DC bias regulator for a cascode amplifier should be capable of enforcing a condition wherein the drain-source voltages for the common-source and common-gate (common-emitter and common-base) transistors are equal by design and remain equal in presence of variation in manufacturing process, temperature and external DC bias voltage.